1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to the mounting of bypass capacitors on a circuit carrier.
2. Description of the Relevant Art
In both analog and digital electronic systems it is necessary to provide power to active devices with a predefined ripple (i.e. low noise). Bypass capacitors are commonly used in electronic circuits in order to xe2x80x9cbypassxe2x80x9d noise caused by the operation of active devices. The use of bypass capacitors may allow an electronic system to have a low impedance in the power distribution system over a wide frequency range (i.e. wideband impedance). An essential factor in achieving wideband impedance is the minimization of attached inductance. Attached inductance is that inductance that may be present in the conductive elements of the capacitor (e.g. capacitor terminals) and the conductive planes to which the capacitor is electrically attached.
FIG. 1 illustrates a current loop that may be affected by the attached inductance for a capacitor that is electrically coupled to a power plane and a ground plane. Capacitor 10 is mounted upon printed circuit board (PCB) 5 at pads 8. One of pads 8 is connected to a ground plane through a first via 9, and the other pad 8 is connected to a power plane through a second via 9.
The current may circulate in a loop and encounter a loop impedance (Zloop). Current may run along the inner contour of the bottom of the capacitor, continuing along the inner sides of the vias, and finally closing in on the plane below. The capacitor may be coupled to a pair of pads. One of the pads may be connected to the ground plane through a first via, while the other pad is connected to the power plane through a second via. In this particular example, the via connecting the second pad to the power plane may pass through an aperture in the ground plane known as an anti-pad.
The loop impedance, Zloop, may be divided into two distinct impedances. The first impedance is a partial impedance through the dielectrics at the location of the anti-pad. The second impedance is the partial impedance encountered through the rest of the current loop. The first partial impedance may be referred to as plane impedance (ZP) and the second partial impedance may be referred to as attached impedance (ZA). The attached impedance may depend on the stack-up and geometry between the capacitor and the closest plane. Attached impedance may be independent of the plane separation, dielectric material between the power and ground planes, and the location on the surface of the plane.
Reduction of the attached inductance may be essential in controlling the impedance of the power distribution system, and may be accomplished by reducing the dimensions of the current loop. The dimensions of the current loop may be reduced by such methods as placing the vias closer together, using capacitors having a thin coating (e.g. the first capacitor plates are closer to the underlying planes), and/or placing the capacitors closer to the planes. The vias may be placed as close together as requirements for center-to-center spacing allow. Capacitor coating thickness may be minimized by using surface-mounted and/or thin-film capacitors. For typical surface-mounted capacitors, the coating thickness may be on the order of 5-15 mils. In thin-film capacitors, the coating thickness may be negligible in comparison with other dimensions in the current loop.
The capacitor itself may be placed closer to the planes when one of the planes is adjacent to the surface. However, considering the surface thickness of the dielectric material covering a plane adjacent to the surface as well as the thickness of the surface metallization, the distance between the bottom surface of the capacitor and the closest plane may still be on the order of several mils. In some instances, it may be possible to remove the dielectric material and assign the outermost metal layer as the power or ground plane. However, this may reduce the effectiveness of the plane, as the plane may be perforated by signal escape traces and their associated connecting pads.
A method of direct plane attachment of capacitors is disclosed. In one embodiment, a printed circuit board (PCB) having a signal layer, a first conductive plane, and a second conductive plane is provided. The signal layer may be the outermost layer of the PCB, while the first conductive layer may be arranged between the signal layer and the second conductive layer. A cavity may be formed in the printed circuit board, wherein the cavity extends from the signal layer down to the first conductive plane. The cavity may be large enough to accommodate one or more capacitors. A first terminal of the capacitor may be attached to the first conductive plane. The second terminal of the capacitor may be mounted within an opening in the first conductive plane. The method may allow a bypass capacitor to be directly coupled to a power or reference plane.
In another embodiment, the cavity may extend from the surface of the PCB to the second conductive plane. A capacitor may be mounted to the PCB within the cavity. The capacitor may include a first terminal attached directly to the first conductive plane and a second terminal attached directly to the second conductive plane.
In various embodiments, the capacitor mounted within the cavity may be a surface mounted capacitor, a thin-film capacitor, or a ball grid array (BGA) type capacitor. The terminals of the capacitor may be connected by soldering, by electrically conductive glue, or a pressure connection. A pressure connection may be formed by placing a capacitor terminal in direct contact with a conductive plane or a via, and holding the capacitor in place with non-conductive glue.
In some embodiments, the first conductive plane may be a ground (or reference) plane while the second conductive plane may be a power plane. In other embodiments, the first conductive plane may be a power plane and the second conductive plane may be a ground plane. The conductive planes may be separated by a layer of dielectric material.
Using the method described herein, a plurality of capacitors may be attached to a conductive plane of a printed circuit board. By attaching capacitors directly to the conductive plane, the dimensions of the current loop may be made smaller, thereby reducing the impedance associated with attached inductance.